사용자 설명서차례DIO 6533 User Manual1Warranty3Copyright3Trademarks3MEDICAL WARNING3Table of Contents4About This Manual9Organization of This Manual9Conventions Used in This Manual10National Instruments Documentation10Related Documentation11Customer Communication12Chapter 1 Introduction13About the DIO 6533 Devices13Using PXI with CompactPCI14What You Need to Get Started15Software Programming Choices16National Instruments Application Software16NI-DAQ Driver Software17Register-Level Programming18Optional Equipment19Unpacking20Chapter 2 Installation and Configuration21Software Installation21Hardware Installation21Installing the PCI-DIO-32HS21Installing the PXI-653322Installing the AT-DIO-32HS23Installing the DAQCard-653323PCI, PXI, and DAQCard Device Configuration24AT Device Configuration25Bus Interface25Plug and Play Mode25Switchless Data Acquisition25Chapter 3 Hardware Overview30Unstrobed I/O33Strobed I/O—Pattern Generation and Handshaking34Pattern and Change Detection35Pattern-Detection Triggers35Change Detection36Message Generation37Handshaking Protocols378255 Emulation38Level ACK38LeadingEdge Pulse38Long Pulse38TrailingEdge Pulse38Burst Mode39Comparing Protocols39Starting a Handshaking Transfer41Controlling the Startup Sequence41Controlling Line Polarities42Transfer Rates42Chapter 4 Signal Connections44I/O Connector44Signal Descriptions46Signal Characteristics49Control Signal Summary50RTSI Bus Interface50Board and RTSI Clocks51RTSI Triggers51Data Signal Connections52Unstrobed I/O53Strobed I/O55Timing Connections56Pull-Up and Pull-Down Connections56Power Connections57Field Wiring and Termination57Chapter 5 Signal Timing60Pattern-Generation Timing60Request Timing61Internal Requests61External Requests61Trigger Timing62Handshake Timing638255 Emulation63Input64Output658255 Emulation Mode Timing Specifications67Other Asynchronous Modes68LevelACK Mode68LeadingEdge Mode73LongPulse Mode78TrailingEdge Mode82Burst Mode86Burst Mode Timing Specifications87Appebdix A Specifications93PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, and DAQCard-6533 Devices93Digital I/O93Strobed I/O95Pattern Generation95Handshaking98Pattern and Change Detection99Triggers99Start and Stop Triggers99RTSI Triggers (PCI, PXI, AT)99Bus Interfaces100Power Requirement100Physical100Environment101Appendix B Optional Adapter Description102Appendix C Customer Communication104Glossary109Index120Figures7Figure 11. The Relationship Between the Programmi...18Figure 21. DAQCard-6533 Completed Installation24Figure 31. PCIDIO32HS/PXI-6533 Block Diagram31Figure 32. ATDIO-32HS Block Diagram32Figure 33. DAQCard-6533 Block Diagram33Figure 34. Pattern Detection Example36Figure 41. 6533 Device I/O Connector Pin Assignme...45Figure 42. RTSI Bus Signal Connection52Figure 43. Example of Data Signal Connections54Figure 44. Transmission Line Terminations59Figure 51. Pattern-Generation Timing60Figure 52. Internal Request Timing61Figure 53. External Request Timing62Figure 54. Trigger Input Signal Timing63Figure 55. 8255 Emulation Mode Input65Figure 56. 8255 Emulation Mode Output66Figure 57. 8255 Emulation Timing67Figure 58. LevelACK Mode Input69Figure 59. LevelACK Mode Output70Figure 510. LevelACK Mode Input Timing71Figure 511. LevelACK Mode Output Timing72Figure 512. LeadingEdge Mode Input74Figure 513. LeadingEdge Mode Output75Figure 514. LeadingEdge Mode Input Timing76Figure 515. LeadingEdge Mode Output Timing77Figure 516. Long-Pulse Mode Input78Figure 517. Long-Pulse Mode Output79Figure 518. LongPulse Mode Input Timing80Figure 519. LongPulse Mode Output Timing81Figure 520. TrailingEdge Mode Input83Figure 521. TrailingEdge Mode Output84Figure 522. TrailingEdge Mode Input Timing85Figure 523. TrailingEdge Mode Output Timing86Figure 524. Input Burst Mode Transfer Example87Figure 525. Output Burst Mode Transfer Example88Figure 526. Burst Mode Output Timing (Default)89Figure 527. Burst Mode Input Timing (Default)90Figure 528. Burst Mode Output Timing (PCLK Revers...91Figure 529. Burst Mode Input Timing (PCLK Reverse...92Figure B1. 68-to-50-Pin Adapter Pin Assignments103Tables8Table 11. Pins Used by the PXI6533 Device15Table 21. PC AT I/O Address Map (Continued)26Table 22. PC AT Interrupt Assignment Map (Continu...28Table 23. PC AT 16Bit DMA Channel Assignment Map...29Table 31. 6533 Handshaking Protocols40Table 41. Signal Descriptions (Continued)46Table 42. Control Signal Summary50크기: 692킬로바이트페이지: 125Language: English매뉴얼 열기
사용자 설명서차례DIO 6533 User Manual1Warranty3Copyright3Trademarks3MEDICAL WARNING3Table of Contents4About This Manual9Organization of This Manual9Conventions Used in This Manual10National Instruments Documentation10Related Documentation11Customer Communication12Chapter 1 Introduction13About the DIO 6533 Devices13Using PXI with CompactPCI14What You Need to Get Started15Software Programming Choices16National Instruments Application Software16NI-DAQ Driver Software17Register-Level Programming18Optional Equipment19Unpacking20Chapter 2 Installation and Configuration21Software Installation21Hardware Installation21Installing the PCI-DIO-32HS21Installing the PXI-653322Installing the AT-DIO-32HS23Installing the DAQCard-653323PCI, PXI, and DAQCard Device Configuration24AT Device Configuration25Bus Interface25Plug and Play Mode25Switchless Data Acquisition25Chapter 3 Hardware Overview30Unstrobed I/O33Strobed I/O—Pattern Generation and Handshaking34Pattern and Change Detection35Pattern-Detection Triggers35Change Detection36Message Generation37Handshaking Protocols378255 Emulation38Level ACK38LeadingEdge Pulse38Long Pulse38TrailingEdge Pulse38Burst Mode39Comparing Protocols39Starting a Handshaking Transfer41Controlling the Startup Sequence41Controlling Line Polarities42Transfer Rates42Chapter 4 Signal Connections44I/O Connector44Signal Descriptions46Signal Characteristics49Control Signal Summary50RTSI Bus Interface50Board and RTSI Clocks51RTSI Triggers51Data Signal Connections52Unstrobed I/O53Strobed I/O55Timing Connections56Pull-Up and Pull-Down Connections56Power Connections57Field Wiring and Termination57Chapter 5 Signal Timing60Pattern-Generation Timing60Request Timing61Internal Requests61External Requests61Trigger Timing62Handshake Timing638255 Emulation63Input64Output658255 Emulation Mode Timing Specifications67Other Asynchronous Modes68LevelACK Mode68LeadingEdge Mode73LongPulse Mode78TrailingEdge Mode82Burst Mode86Burst Mode Timing Specifications87Appebdix A Specifications93PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, and DAQCard-6533 Devices93Digital I/O93Strobed I/O95Pattern Generation95Handshaking98Pattern and Change Detection99Triggers99Start and Stop Triggers99RTSI Triggers (PCI, PXI, AT)99Bus Interfaces100Power Requirement100Physical100Environment101Appendix B Optional Adapter Description102Appendix C Customer Communication104Glossary109Index120Figures7Figure 11. The Relationship Between the Programmi...18Figure 21. DAQCard-6533 Completed Installation24Figure 31. PCIDIO32HS/PXI-6533 Block Diagram31Figure 32. ATDIO-32HS Block Diagram32Figure 33. DAQCard-6533 Block Diagram33Figure 34. Pattern Detection Example36Figure 41. 6533 Device I/O Connector Pin Assignme...45Figure 42. RTSI Bus Signal Connection52Figure 43. Example of Data Signal Connections54Figure 44. Transmission Line Terminations59Figure 51. Pattern-Generation Timing60Figure 52. Internal Request Timing61Figure 53. External Request Timing62Figure 54. Trigger Input Signal Timing63Figure 55. 8255 Emulation Mode Input65Figure 56. 8255 Emulation Mode Output66Figure 57. 8255 Emulation Timing67Figure 58. LevelACK Mode Input69Figure 59. LevelACK Mode Output70Figure 510. LevelACK Mode Input Timing71Figure 511. LevelACK Mode Output Timing72Figure 512. LeadingEdge Mode Input74Figure 513. LeadingEdge Mode Output75Figure 514. LeadingEdge Mode Input Timing76Figure 515. LeadingEdge Mode Output Timing77Figure 516. Long-Pulse Mode Input78Figure 517. Long-Pulse Mode Output79Figure 518. LongPulse Mode Input Timing80Figure 519. LongPulse Mode Output Timing81Figure 520. TrailingEdge Mode Input83Figure 521. TrailingEdge Mode Output84Figure 522. TrailingEdge Mode Input Timing85Figure 523. TrailingEdge Mode Output Timing86Figure 524. Input Burst Mode Transfer Example87Figure 525. Output Burst Mode Transfer Example88Figure 526. Burst Mode Output Timing (Default)89Figure 527. Burst Mode Input Timing (Default)90Figure 528. Burst Mode Output Timing (PCLK Revers...91Figure 529. Burst Mode Input Timing (PCLK Reverse...92Figure B1. 68-to-50-Pin Adapter Pin Assignments103Tables8Table 11. Pins Used by the PXI6533 Device15Table 21. PC AT I/O Address Map (Continued)26Table 22. PC AT Interrupt Assignment Map (Continu...28Table 23. PC AT 16Bit DMA Channel Assignment Map...29Table 31. 6533 Handshaking Protocols40Table 41. Signal Descriptions (Continued)46Table 42. Control Signal Summary50크기: 692킬로바이트페이지: 125Language: English매뉴얼 열기