Manuel D’UtilisationTable des matièresMVME25001Contents3About this Manual13Overview of Contents13Abbreviations13Conventions15Summary of Changes17Introduction191.1 Overview191.2 Standard Compliances211.3 Mechanical Data221.4 Ordering Information221.5 Product Identification24Hardware Preparation and Installation252.1 Overview252.2 Unpacking and Inspecting the Board262.3 Requirements262.3.1 Environmental Requirements272.3.2 Power Requirements282.3.3 Equipment Requirements292.4 Configuring the Board292.5 Installing Accessories302.5.1 Rear Transition Module302.5.2 PMC/XMC Support312.6 Installing and Removing the Board322.7 Completing the Installation34Controls, LEDs, and Connectors353.1 Board Layout353.2 Front Panel363.2.1 Reset Switch373.3 LEDs373.3.1 Front Panel LEDs373.3.2 Onboard LEDs393.4 Connectors393.4.1 Front Panel Connectors403.4.1.1 RJ45 with Integrated Magnetics (J1)403.4.1.2 Front Panel Serial Port (J4)413.4.1.3 USB Connector (J5)423.4.1.4 VMEBus P1 Connector423.4.1.5 VMEBus P2 Connector443.4.2 Onboard Connectors453.4.2.1 Flash Program Connector (P7)453.4.2.2 SATA Connector (J3)463.4.2.3 PMC Connectors473.4.2.4 JTAG Connector (P6)523.4.2.5 COP Connector (P6)543.4.2.6 SD Connector (J2)543.4.2.7 XMC Connector (XJ2)553.4.2.8 Miscellaneous P2020 Debug Connectors563.5 Switches573.5.1 Geographical Address Switch (S1)573.5.2 SMT Configuration Switch (S2)59Functional Description614.1 Block Diagram614.2 Chipset614.2.1 e500 Processor Core624.2.2 Integrated Memory Controller624.2.3 PCI Express Interface634.2.4 Local Bus Controller (LBC)634.2.5 Secure Digital Hub Controller (SDHC)634.2.6 I2C Interface634.2.7 USB Interface634.2.8 DUART644.2.9 DMA Controller644.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)644.2.11 General Purpose I/O (GPIO)644.2.12 Security Engine (SEC) 3.1644.2.13 Common On-Chip Processor (COP)654.2.14 P20x0 Hardware Configuration Pins654.3 System Memory654.4 Timers654.4.1 Real Time Clock654.4.2 Internal Timer664.4.3 Watchdog Timer664.4.4 FPGA Tick Timer664.5 Ethernet Interfaces664.6 SPI Bus Interface674.6.1 SPI Flash Memory674.6.2 SPI Flash Programming674.6.3 Firmware Redundancy684.6.4 Crisis Recovery704.7 Front UART Control704.8 Rear UART Control714.9 PMC/XMC Sites714.9.1 PMC Add-on Card724.9.2 XMC Add-on Card724.10 SATA Interface724.11 VME Support734.11.1 Tsi148 VME Controller734.12 USB734.13 I2C Devices734.14 Reset/Control FPGA744.15 Power Management744.15.1 Onboard Voltage Supply Requirement744.15.2 Power Up Sequencing Requirements754.16 Clock Structure764.17 Reset Structure764.17.1 Reset Sequence774.18 Thermal Management774.19 Real-Time Clock Battery774.20 Debugging Support784.20.1 POST Code Indicator784.20.2 JTAG Chain and Board784.20.3 Custom Debugging794.21 Rear Transition Module (RTM)79Memory Maps and Registers815.1 Overview815.2 Memory Map815.3 Flash Memory Map825.4 Linux Devices Memory Map825.5 Programmable Logic Device (PLD) Registers845.5.1 PLD Revision Register845.5.2 PLD Year Register845.5.3 PLD Month Register855.5.4 PLD Day Register855.5.5 PLD Sequence Register855.5.6 PLD Power Good Monitor Register865.5.7 PLD LED Control Register875.5.8 PLD PCI/PMC/XMC Monitor Register885.5.9 PLD U-Boot and TSI Monitor Register895.5.10 PLD Boot Bank Register895.5.11 PLD Write Protect and I2C Debug Register915.5.12 PLD Test Register 1935.5.13 PLD Test Register 2935.5.14 PLD GPIO2 Interrupt Register945.5.15 PLD Shutdown and Reset Control and Reset Reason Register955.5.16 PLD Watchdog Timer Refresh Register965.5.17 PLD Watchdog Control Register975.5.18 PLD Watchdog Timer Count Register975.6 External Timer Registers985.6.1 Prescaler Register985.6.2 Control Registers995.6.3 Compare High and Low Word Registers1005.6.4 Counter High and Low Word Registers101Boot System1036.1 Overview1036.2 Accessing U-Boot1036.3 Boot Options1046.3.1 Booting from a Network1046.3.2 Booting from an Optional SATA Drive1056.3.3 Booting from a USB Drive1056.3.4 Booting from an SD Card1066.3.5 Booting VxWorks Through the Network1066.4 Using the Persistent Memory Feature1076.5 MVME2500 Specific U-Boot Commands1086.6 Updating U-Boot110Programming Model1137.1 Overview1137.2 Reset Configuration1137.3 Interrupt Controller1177.4 I2C Bus Device Addressing1187.5 Ethernet PHY Address1187.6 Other Software Considerations1197.6.1 MRAM1197.6.2 Real Time Clock1197.6.3 Quad UART1197.6.4 LBC Timing Parameters1207.7 Clock Distribution1217.7.1 System Clock1227.7.2 Real Time Clock Input1237.7.3 Local Bus Controller Clock Divisor123A Replacing the Battery125A.1 Replacing the Battery125B Related Documentation129B.1 Emerson Network Power - Embedded Computing Documents129B.2 Manufacturers’ Documents130B.3 Related Specifications130Safety Notes133Sicherheitshinweise137Index143Taille: 2,9 MoPages: 146Language: EnglishOuvrir le manuel