Data SheetTable of ContentsHigh-Performance 32-bit RISC CPU:3Microcontroller Features:3Peripheral Features:3Debug Features:3Analog Features:3Pin Diagrams6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)12Pin Diagrams (Continued)13Pin Diagrams (Continued)14Pin Diagrams (Continued)15Table of Contents18Most Current Data Sheet19Errata19Customer Notification System191.0 Device Overview21FIGURE 1-1: Block Diagram(1,2)21Table 1-1: Pinout I/O Descriptions (Continued)222.0 Guidelines for Getting Started with 32-bit Microcontrollers312.1 Basic Connection Requirements312.2 Decoupling Capacitors31FIGURE 2-1: Recommended Minimum Connection322.2.1 Bulk Capacitors322.3 Capacitor on Internal Voltage Regulator (Vcap/Vcore)322.3.1 Internal Regulator Mode322.3.2 External Regulator Mode322.4 Master Clear (MCLR) Pin32FIGURE 2-2: Example of MCLR Pin Connections322.5 ICSP Pins332.6 JTAG332.7 Trace332.8 External Oscillator Pins33FIGURE 2-3: Suggested Placement of the Oscillator Circuit332.9 Configuration of Analog and Digital Pins During ICSP Operations342.10 Unused I/Os342.11 Referenced Sources353.0 CPU373.1 Features37FIGURE 3-1: MIPS® M4K® Block Diagram373.2 Architecture Overview383.2.1 Execution Unit383.2.2 Multiply/Divide Unit (MDU)38Table 3-1: MIPS® M4K® Processor Core High-Performance Integer Multiply/Divide Unit Latencies and Repeat Rates393.2.3 System Control Coprocessor (CP0)39Table 3-2: Coprocessor 0 Registers (Continued)39Table 3-3: PIC32MX3XX/4XX family Core Exception Types403.3 Power Management413.3.1 Instruction-Controlled Power Management413.3.2 Local Clock Gating413.4 EJTAG Debug Support414.0 Memory Organization434.1 Key Features434.2 PIC32MX3XX/4XX Memory Layout43Figure 4-1: Memory Map on Reset for PIC32MX320F032H and PIC32MX420F032H Devices(1)44Figure 4-2: Memory Map on Reset for PIC32MX320F064H Device(1)45Figure 4-3: Memory Map on Reset for PIC32MX320F128H and PIC32MX320F128L Devices(1)46Figure 4-4: Memory Map on Reset for PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H and PIC32MX440F128L Devices(1)47Figure 4-5: Memory Map on Reset for PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H and PIC32MX460F256L Devices(1)48Figure 4-6: Memory Map on Reset for PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H and PIC32MX460F512L Devices(1)49TABLE 4-1: Bus Matrix Registers Map50TABLE 4-2: Interrupt Registers Map for PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)51Table 4-3: Interrupt Registers Map for PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, PIC32MX360F256L and PIC32MX360F512L Devices Only(1)52Table 4-4: Interrupt Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H and PIC32MX320F128L Devices Only(1)53Table 4-5: Interrupt Registers Map for PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)54Table 4-6: Interrupt Registers Map for the PIC32MX420F032H Device Only(1)55TABLE 4-7: Timer1-5 Registers Map(1)56TABLE 4-8: Input Capture1-5 Registers Map57TABLE 4-9: Output Compare1-5 Registers Map(1)58TABLE 4-10: I2C1-2 Registers Map(1)59TABLE 4-11: UART1-2 Registers Map60TABLE 4-12: SPI1-2 Registers Map(1,2)61TABLE 4-13: ADC Registers Map (Continued)62TABLE 4-14: DMA Global Registers Map for PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX Devices Only64TABLE 4-15: DMA CRC Registers Map for PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX Devices Only(1)64TABLE 4-16: DMA Channels 0-3 Registers Map for PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX Devices Only(1) (Continued)65TABLE 4-17: Comparator Registers Map(1)68TABLE 4-18: Comparator Voltage Reference Registers Map(1)68TABLE 4-19: Flash Controller Registers Map69TABLE 4-20: System Control Registers Map(1,2)69TABLE 4-21: PortA Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)70TABLE 4-22: PortB Registers Map(1)70TABLE 4-23: PortC Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)71TABLE 4-24: PortC Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)71TABLE 4-25: PortD Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)72TABLE 4-26: PortD Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)72TABLE 4-27: PortE Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)73TABLE 4-28: PortE Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)73TABLE 4-29: PortF Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L and PIC32MX360F512L Devices Only(1)74TABLE 4-30: PortF Registers Map for PIC32MX440f128l, pic32mx460f256l AND pic32mx460f512l Devices Only(1)74TABLE 4-31: PortF Registers Map for PIC32MX320f032h, pic32mx320f064h, pic32mx320f128h, pic32mx340f128h, pic32mx340f256h AND pic32mx340f512h Devices Only(1)75TABLE 4-32: PortF Registers Map for PIC32MX420f032h, pic32mx440f128h and pic2mx440f256h Devices Only(1)75TABLE 4-33: PortG Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)76TABLE 4-34: PortG Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)76TABLE 4-35: Change Notice and Pull-Up Registers Map for PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices Only(1)77TABLE 4-36: Change Notice and Pull-Up Registers Map for PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H and PIC32MX440F512H Devices Only(1)77TABLE 4-37: Parallel Master Port Registers Map(1)78TABLE 4-38: Programming and Diagnostics Registers Map78TABLE 4-39: Prefetch Registers Map79TABLE 4-40: RTCC Registers Map(1)80TABLE 4-41: DEVCFG: Device Configuration Word Summary80TABLE 4-42: Device and Revision ID Summary81TABLE 4-43: USB Registers Map(1) (Continued)825.0 Flash Program Memory85EXAMPLE 5-1:856.0 Resets87FIGURE 6-1: System Reset Block Diagram877.0 Interrupt Controller89FIGURE 7-1: Interrupt Controller Module89Table 7-1: Interrupt IRQ and Vector Location (Continued)908.0 Oscillator Configuration93FIGURE 8-1: PIC32MX3XX/4XX Family Clock Diagram939.0 Prefetch Cache959.1 Features95FIGURE 9-1: Prefetch Module Block Diagram9510.0 Direct Memory Access (DMA) Controller97FIGURE 10-1: DMA Block Diagram9711.0 USB On-The-Go (OTG)99FIGURE 11-1: PIC32MX3XX/4XX Family USB Interface Diagram10012.0 I/O Ports101FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure10112.1 Parallel I/O (PIO) Ports10212.1.1 CLR, SET and INV Registers10212.1.2 Digital Inputs10212.1.3 Analog Inputs10212.1.4 Digital Outputs10212.1.5 Analog Outputs10212.1.6 Input Change Notification10213.0 Timer110313.1 Additional Supported Features103FIGURE 13-1: Timer1 Block Diagram(1)10314.0 Timer2/3 and Timer4/510514.1 Additional Supported Features105FIGURE 14-1: Timer2, 3, 4, 5 Block Diagram (16-bit)105FIGURE 14-2: Timer2/3, 4/5 Block Diagram (32-bit)10615.0 Input Capture107FIGURE 15-1: Input Capture Block Diagram10716.0 Output Compare109FIGURE 16-1: Output Compare Module Block Diagram10917.0 Serial Peripheral Interface (SPI)111FIGURE 17-1: SPI Module Block Diagram11118.0 Inter-Integrated Circuit™ (I2C™)113FIGURE 18-1: I2C™ Block Diagram (x = 1 or 2)11419.0 Universal Asynchronous Receiver Transmitter (UART)115FIGURE 19-1: UART Simplified Block Diagram115FIGURE 19-2: Transmission (8-Bit or 9-Bit Data)116FIGURE 19-3: Two Consecutive Transmissions116FIGURE 19-4: UART Reception117FIGURE 19-5: UART Reception with Receive Overrun11720.0 Parallel Master Port (PMP)119FIGURE 20-1: PMP Module Pinout and Connections to External Devices11921.0 Real-Time Clock and Calendar (RTCC)121FIGURE 21-1: RTCC Block Diagram12122.0 10-bit Analog-to-Digital Converter (ADC)123FIGURE 22-1: ADC1 Module Block Diagram123FIGURE 22-2: ADC Conversion Clock Period Block Diagram12423.0 Comparator125FIGURE 23-1: Comparator Block Diagram12524.0 Comparator Voltage Reference (CVref)127FIGURE 24-1: Comparator Voltage Reference Block Diagram12725.0 Power-Saving Features12925.1 Power-Saving with CPU Running12925.2 CPU Halted Methods12925.3 Power-Saving Operation12925.3.1 Sleep Mode12925.3.2 Idle Mode13025.3.3 Peripheral Bus Scaling Method13026.0 Special Features13126.1 Configuration Bits131Register 26-1: DEVCFG0: Device Configuration Word 0 (Continued)131Register 26-2: DEVCFG1: Device Configuration Word 1 (Continued)133Register 26-3: DEVCFG2: Device Configuration Word 2135Register 26-4: DEVCFG3: Device Configuration Word 3136Register 26-5: DEVID: Device and Revision ID Register13626.2 Watchdog Timer (WDT)137Figure 26-1: Watchdog and Power-Up Timer Block Diagram13726.3 On-Chip Voltage Regulator13826.3.1 On-Chip Regulator and POR13826.3.2 On-Chip Regulator and BOR13826.3.3 Power-up Requirements138Figure 26-2: Connections for the On-Chip Regulator13826.4 Programming and Diagnostics139FIGURE 26-3: Block Diagram of Programming, Debugging and Trace Ports139Register 26-6: DDPCON: Debug Data Port Control Register14027.0 Instruction Set141Table 27-1: MIPS32® Instruction Set14128.0 Development Support14728.1 MPLAB Integrated Development Environment Software14728.2 MPLAB C Compilers for Various Device Families14828.3 HI-TECH C for Various Device Families14828.4 MPASM Assembler14828.5 MPLINK Object Linker/ MPLIB Object Librarian14828.6 MPLAB Assembler, Linker and Librarian for Various Device Families14828.7 MPLAB SIM Software Simulator14928.8 MPLAB REAL ICE In-Circuit Emulator System14928.9 MPLAB ICD 3 In-Circuit Debugger System14928.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express14928.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express15028.12 MPLAB PM3 Device Programmer15028.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits15029.0 Electrical Characteristics151Absolute Maximum Ratings151(Note 1)15129.1 DC Characteristics152Table 29-1: Operating MIPS vs. Voltage152Table 29-2: Thermal Operating Conditions152Table 29-3: Thermal Packaging Characteristics152Table 29-4: DC Temperature and Voltage Specifications152Table 29-5: DC Characteristics: Operating Current (Idd)153Table 29-6: DC Characteristics: Idle Current (Iidle)154Table 29-7: DC Characteristics: Power-Down Current (Ipd) (Continued)155Table 29-8: DC Characteristics: I/O Pin Input Specifications157Table 29-9: DC Characteristics: I/O Pin Output Specifications158Table 29-10: Electrical Characteristics: Brown-Out Reset (BOR)158Table 29-11: DC Characteristics: Program Memory(3)159Table 29-12: Program Flash Memory Wait State Characteristics159Table 29-13: Comparator Specifications160Table 29-14: Voltage Reference Specifications160Table 29-15: Internal Voltage Regulator Specifications16029.2 AC Characteristics and Timing Parameters161Figure 29-1: Load Conditions for Device Timing Specifications161Table 29-16: Capacitive Loading Requirements on Output Pins161Figure 29-2: External Clock Timing161Table 29-17: External Clock Timing Requirements162Table 29-18: PLL Clock Timing Specifications (Vdd = 2.3V to 3.6V)163Table 29-19: Internal FRC Accuracy163Table 29-20: Internal RC Accuracy163Figure 29-3: I/O Timing Characteristics164Table 29-21: I/O Timing Requirements164Figure 29-4: Power-On Reset Timing Characteristics165Figure 29-5: External Reset Timing Characteristics166Table 29-22: Resets Timing166Figure 29-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics167Table 29-23: Timer1 External Clock Timing Requirements(1)167Table 29-24: Timer2, 3, 4, 5 External Clock Timing Requirements168Figure 29-7: Input Capture (CAPx) Timing Characteristics169Table 29-25: Input Capture Module Timing Requirements169Figure 29-8: Output Compare Module (OCx) Timing Characteristics169Table 29-26: Output Compare Module Timing Requirements169Figure 29-9: OC/PWM Module Timing Characteristics170Table 29-27: Simple OC/PWM MODE Timing Requirements170Figure 29-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics171Table 29-28: SPIx Master Mode (CKE = 0) Timing Requirements171Figure 29-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics172Table 29-29: SPIx Module Master Mode (CKE = 1) Timing Requirements172Figure 29-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics173Table 29-30: SPIx Module Slave Mode (CKE = 0) Timing Requirements173Figure 29-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics174Table 29-31: SPIx Module Slave Mode (CKE = 1) Timing Requirements174Figure 29-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)175Figure 29-15: I2Cx Bus Data Timing Characteristics (Master Mode)175Table 29-32: I2Cx Bus Data Timing Requirements (Master Mode)176Figure 29-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)177Figure 29-17: I2Cx Bus Data Timing Characteristics (Slave Mode)177Table 29-33: I2Cx Bus Data Timing Requirements (Slave Mode)178Table 29-34: ADC Module Specifications (Continued)179Table 29-35: 10-bit ADC Conversion Rate Parameters(2)181Table 29-36: Analog-to-Digital Conversion Timing Requirements182Figure 29-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)183Figure 29-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)184Figure 29-20: Parallel Slave Port Timing185Table 29-37: Parallel Slave Port Requirements185Figure 29-21: Parallel Master Port Read Timing Diagram186Table 29-38: Parallel Master Port Read Timing Requirements186Figure 29-22: Parallel Master Port Write Timing Diagram187Table 29-39: Parallel Master Port Write Timing Requirements187Table 29-40: OTG Electrical Specifications188Figure 29-23: EJTAG Timing Characteristics189Table 29-41: EJTAG Timing Requirements18930.0 Packaging Information19130.1 Package Marking Information19130.2 Package Details192Appendix A: Revision History203Revision E (July 2008)203Revision F (June 2009)203TABLE A-1: Major Section Updates (Continued)203Revision G (April 2010)205TABLE A-2: Major Section Updates (Continued)205Revision H (May 2011)207TABLE A-3: Major Section Updates (Continued)207Index209The Microchip Web Site211Customer Change Notification Service211Customer Support211Reader Response212Product Identification System213Worldwide Sales and Service214Size: 4 MBPages: 214Language: EnglishOpen manual