User ManualTable of ContentsCHAPTER 1 FR FAMILY OVERVIEW251.1 Features of the FR Family CPU Core261.2 Sample Configuration of an FR Family Device271.3 Sample Configuration of the FR Family CPU28CHAPTER 2 MEMORY ARCHITECTURE292.1 FR Family Memory Space302.1.1 Direct Address Area312.1.2 Vector Table Area322.2 Bit Order and Byte Order342.3 Word Alignment35CHAPTER 3 REGISTER DESCRIPTIONS373.1 FR Family Register Configuration383.2 General-purpose Registers393.3 Dedicated Registers413.3.1 Program Counter (PC)423.3.2 Program Status (PS)433.3.3 Table Base Register (TBR)473.3.4 Return Pointer (RP)493.3.5 System Stack Pointer (SSP), User Stack Pointer (USP)513.3.6 Multiplication/Division Register (MD)53CHAPTER 4 RESET AND "EIT" PROCESSING554.1 Reset Processing574.2 Basic Operations in "EIT" Processing584.3 Interrupts614.3.1 User Interrupts624.3.2 Non-maskable Interrupts (NMI)644.4 Exception Processing664.4.1 Undefined Instruction Exceptions674.5 Traps684.5.1 "INT" Instructions694.5.2 "INTE" Instruction704.5.3 Step Trace Traps714.5.4 Coprocessor Not Found Traps724.5.5 Coprocessor Error Trap734.6 Priority Levels75CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU775.1 Pipeline Operation785.2 Pipeline Operation and Interrupt Processing795.3 Register Hazards805.4 Delayed Branching Processing825.4.1 Processing Non-delayed Branching Instructions845.4.2 Processing Delayed Branching Instructions85CHAPTER 6 INSTRUCTION OVERVIEW876.1 Instruction Formats886.2 Instruction Notation Formats90CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS917.1 ADD (Add Word Data of Source Register to Destination Register)967.2 ADD (Add 4-bit Immediate Data to Destination Register)977.3 ADD2 (Add 4-bit Immediate Data to Destination Register)987.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)997.5 ADDN (Add Word Data of Source Register to Destination Register)1007.6 ADDN (Add Immediate Data to Destination Register)1017.7 ADDN2 (Add Immediate Data to Destination Register)1027.8 SUB (Subtract Word Data in Source Register from Destination Register)1037.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)1047.10 SUBN (Subtract Word Data in Source Register from Destination Register)1057.11 CMP (Compare Word Data in Source Register and Destination Register)1067.12 CMP (Compare Immediate Data of Source Register and Destination Register)1077.13 CMP2 (Compare Immediate Data and Destination Register)1087.14 AND (And Word Data of Source Register to Destination Register)1097.15 AND (And Word Data of Source Register to Data in Memory)1107.16 ANDH (And Half-word Data of Source Register to Data in Memory)1127.17 ANDB (And Byte Data of Source Register to Data in Memory)1147.18 OR (Or Word Data of Source Register to Destination Register)1167.19 OR (Or Word Data of Source Register to Data in Memory)1177.20 ORH (Or Half-word Data of Source Register to Data in Memory)1197.21 ORB (Or Byte Data of Source Register to Data in Memory)1217.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)1237.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)1247.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)1267.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)1287.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)1307.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)1327.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)1347.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)1367.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)1387.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)1407.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory)1427.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory)1437.34 MUL (Multiply Word Data)1447.35 MULU (Multiply Unsigned Word Data)1467.36 MULH (Multiply Half-word Data)1487.37 MULUH (Multiply Unsigned Half-word Data)1507.38 DIV0S (Initial Setting Up for Signed Division)1527.39 DIV0U (Initial Setting Up for Unsigned Division)1547.40 DIV1 (Main Process of Division)1567.41 DIV2 (Correction when Remainder is 0)1587.42 DIV3 (Correction when Remainder is 0)1607.43 DIV4S (Correction Answer for Signed Division)1617.44 LSL (Logical Shift to the Left Direction)1627.45 LSL (Logical Shift to the Left Direction)1637.46 LSL2 (Logical Shift to the Left Direction)1647.47 LSR (Logical Shift to the Right Direction)1657.48 LSR (Logical Shift to the Right Direction)1667.49 LSR2 (Logical Shift to the Right Direction)1677.50 ASR (Arithmetic Shift to the Right Direction)1687.51 ASR (Arithmetic Shift to the Right Direction)1697.52 ASR2 (Arithmetic Shift to the Right Direction)1707.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)1717.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)1727.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)1737.56 LD (Load Word Data in Memory to Register)1747.57 LD (Load Word Data in Memory to Register)1757.58 LD (Load Word Data in Memory to Register)1767.59 LD (Load Word Data in Memory to Register)1777.60 LD (Load Word Data in Memory to Register)1787.61 LD (Load Word Data in Memory to Register)1797.62 LD (Load Word Data in Memory to Program Status Register)1817.63 LDUH (Load Half-word Data in Memory to Register)1837.64 LDUH (Load Half-word Data in Memory to Register)1847.65 LDUH (Load Half-word Data in Memory to Register)1857.66 LDUB (Load Byte Data in Memory to Register)1867.67 LDUB (Load Byte Data in Memory to Register)1877.68 LDUB (Load Byte Data in Memory to Register)1887.69 ST (Store Word Data in Register to Memory)1897.70 ST (Store Word Data in Register to Memory)1907.71 ST (Store Word Data in Register to Memory)1917.72 ST (Store Word Data in Register to Memory)1927.73 ST (Store Word Data in Register to Memory)1937.74 ST (Store Word Data in Register to Memory)1947.75 ST (Store Word Data in Program Status Register to Memory)1957.76 STH (Store Half-word Data in Register to Memory)1967.77 STH (Store Half-word Data in Register to Memory)1977.78 STH (Store Half-word Data in Register to Memory)1987.79 STB (Store Byte Data in Register to Memory)1997.80 STB (Store Byte Data in Register to Memory)2007.81 STB (Store Byte Data in Register to Memory)2017.82 MOV (Move Word Data in Source Register to Destination Register)2027.83 MOV (Move Word Data in Source Register to Destination Register)2037.84 MOV (Move Word Data in Program Status Register to Destination Register)2047.85 MOV (Move Word Data in Source Register to Destination Register)2057.86 MOV (Move Word Data in Source Register to Program Status Register)2067.87 JMP (Jump)2087.88 CALL (Call Subroutine)2097.89 CALL (Call Subroutine)2107.90 RET (Return from Subroutine)2117.91 INT (Software Interrupt)2127.92 INTE (Software Interrupt for Emulator)2147.93 RETI (Return from Interrupt)2167.94 Bcc (Branch Relative if Condition Satisfied)2187.95 JMP:D (Jump)2207.96 CALL:D (Call Subroutine)2217.97 CALL:D (Call Subroutine)2237.98 RET:D (Return from Subroutine)2257.99 Bcc:D (Branch Relative if Condition Satisfied)2277.100 DMOV (Move Word Data from Direct Address to Register)2297.101 DMOV (Move Word Data from Register to Direct Address)2307.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)2317.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)2337.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address)2357.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)2377.106 DMOVH (Move Half-word Data from Direct Address to Register)2397.107 DMOVH (Move Half-word Data from Register to Direct Address)2407.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address)2417.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)2437.110 DMOVB (Move Byte Data from Direct Address to Register)2457.111 DMOVB (Move Byte Data from Register to Direct Address)2467.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)2477.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)2497.114 LDRES (Load Word Data in Memory to Resource)2517.115 STRES (Store Word Data in Resource to Memory)2527.116 COPOP (Coprocessor Operation)2537.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)2557.118 COPST (Store 32-bit Data from Coprocessor Register to Register)2577.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)2597.120 NOP (No Operation)2617.121 ANDCCR (And Condition Code Register and Immediate Data)2627.122 ORCCR (Or Condition Code Register and Immediate Data)2637.123 STILM (Set Immediate Data to Interrupt Level Mask Register)2647.124 ADDSP (Add Stack Pointer and Immediate Data)2657.125 EXTSB (Sign Extend from Byte Data to Word Data)2667.126 EXTUB (Unsign Extend from Byte Data to Word Data)2677.127 EXTSH (Sign Extend from Byte Data to Word Data)2687.128 EXTUH (Unsigned Extend from Byte Data to Word Data)2697.129 LDM0 (Load Multiple Registers)2707.130 LDM1 (Load Multiple Registers)2727.131 STM0 (Store Multiple Registers)2747.132 STM1 (Store Multiple Registers)2767.133 ENTER (Enter Function)2787.134 LEAVE (Leave Function)2807.135 XCHB (Exchange Byte Data)282APPENDIX285APPENDIX A Instruction Lists286A.1 Symbols Used in Instruction Lists287A.2 Instruction Lists289APPENDIX B Instruction Maps298B.1 Instruction Map299B.2 "E" Format300INDEX301A302B302C303D303E305F305G305H306I306J307L307M308N309O309P309R309S310T312U312V312W312X312Size: 5.34 MBPages: 314Language: EnglishOpen manual